Dual buck-boost converter with single inductor

ABSTRACT

A dual output buck-boost power converter operates with a single inductor to achieve high efficiency with automatic or inherent load balancing. Switches associated with the opposite polarity outputs are driven based on feedback signals, with one feedback signal being a reference voltage and another feedback signal being related to an opposite polarity output. The opposite polarity feedback signal is provided to a comparator with a reversed polarity to achieve a simple balanced control that maintains polarity outputs. The power converter delivers power to each output with each switching cycle and uses a single inductor to achieve high efficiency performance.

CROSS REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to power converters, and relatesmore particularly to a dual buck-boost power converter with independentregulation.

2. Description of Related Art

Dual buck-boost converter topologies are available for a number ofapplications. Typically, two different power supplies create twoseparate outputs. The two separate outputs are often a positive voltageoutput and a negative voltage output.

Referring to FIG. 1, a buck-boost converter with two inputs and twooutputs is illustrated as circuit 10. Circuit 10 includes two of eachcomponent, such as two switches S1, S2, two diodes D1, D2, two inductorsL1, L2 and two capacitors C1, C2. The two power supplies, indicated ascircuit 12 and 13, each have a separate feedback circuit to provide aclosed loop control. Circuit 12 and 13 each use a reference voltage inconjunction with a feedback voltage value to determine modulation of thevoltage to duty cycle conversion. In circuit 10, two separate inputs of+/−5V are used to generate the two separate outputs, +Vout and −Vout. Inaddition, there are typically two separate loads, negative load 14 andpositive load 15.

In circuit 10, switches S1 and S2 are operated to control power outputto loads 14 and 15 according to the desired set point determined byvoltage Vref. In controlling the output to loads 14 and 15, inductors L1and L2 are separately charged or discharged. Accordingly, circuit 10uses two separate inductors that typically are realized as externalcomponents due to their size. That is, the majority of components incircuit 10 can be formed in an integrated circuit with the notedexception of inductors L1 and L2. The use of two inductors also addscost to the circuit in terms of component cost and increased size thatis realized in constructing the converter.

An alternative to circuit 10 provides a buck-boost converter that drivesa positive and negative output voltage on alternating cycles of thecontroller respectively. This alternate method uses one inductor, butsuffers from being less efficient in power density and deviceutilization. The outputs of this alternative prior circuit using asingle inductor also has very high ripple voltage on both outputs +Voutand −Vout.

In some buck-boost solutions that deliver dual outputs, a load balanceris sometimes used to help maintain the output voltages at consistent andopposite levels. However, the load balancer typically draws extra powerby shunting voltage or current, and reduces the overall efficiency ofthe power converter.

Accordingly, it would be desirable to obtain a buck-boost converter witha dual output and single inductor with improved efficiency andperformance.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a dualoutput buck-boost converter with a single inductor and independentlyregulated outputs. According to an exemplary embodiment, the buck-boostconverter has two inputs and two outputs. The inputs are switched inaccordance with a duty cycle control to regulate output voltage. Afeedback comparison for the converter uses a pre-specified voltagereference for one of the voltage outputs, and uses an output dependentvoltage references for another of the outputs. The duty cycle control isgenerated based on the comparison with the reference voltages, so thatthe duty cycle for one switch is based on a pre-specified referencevoltage, while the duty cycle of another switch is based on a comparisonwith an output voltage. The feedback control configuration providesinherent or automatic load balancing and adjustments to variations ininput voltage supplies.

According to an advantage of the present invention, a surge at either ofthe power converter outputs is balanced and corrected within a fewcontrol cycles where the input switches are appropriately switched. Inaddition, if either of the outputs sags below a desired value, thechange is compensated and corrected within several control cycles byappropriately switching the input switches. The input switches can havediffering on times to adjust the positive or negative output voltage.

According to an aspect of the present invention, the power converterruns in discontinuous mode. A switch duty cycle is modified during acontrol cycle to compensate variations in output voltages for either anegative or positive output voltage.

According to another aspect of the present invention, the input switchesare complementary bipolar switches. In accordance with a particularembodiment of the present invention, the switches and other solid statedevices, such as diodes, for example, are contained within an integratedcircuit (IC), that also includes control circuitry. In accordance withthis embodiment, power capacitors and a single inductor are supplied asexternal components to the IC.

According to another aspect of the present invention, a PNP switch on aninput to the power converter is switched off earlier or later than anNPN switch on another input to the power converter. The switches arecoupled together through a single inductor, and are operated to providepower to the high and low side outputs in every switching cycle.

According to a method of the present invention, pulse widths of a singleswitching operation are increased to increase output voltage, anddecreased to decrease output voltage. If a positive voltage outputbecomes higher than the corresponding negative voltage output, the inputswitch for the negative voltage receives a shorter width pulse. If thenegative voltage becomes higher than the corresponding positive voltageoutput, the input switch associated with the negative output receives alonger width pulse. With this control method, the load is automaticallybalanced between the two outputs and a single inductor can be used.

In accordance with another aspect of the present invention, powerconverter input switches are controlled based on a differential andcommon mode feedback signal, applied to separate polarity inputswitching controls. One polarity switch operates based on a differentialmode feedback signal, while the other polarity input operates on acommon mode feedback signal. By providing the two different modes offeedback with the different polarities, the output of the powerconverter can be inherently or automatically balanced.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The features and advantages of the present invention will becomeapparent from the following description read in conjunction with theaccompanying drawings, in which:

FIG. 1 is a circuit block diagram of a conventional dual outputbuck-boost converter;

FIG. 2 is a circuit block diagram of an embodiment of a dual outputbuck-boost converter in accordance with the present invention;

FIG. 3 is a circuit block diagram of another embodiment of a dual outputbuck-boost converter in accordance with the present invention; and

FIG. 4 is a set of graphs illustrating switching operations for pulsewidth control in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 2, a circuit block diagram of a dual buck-boostconverter in accordance with the present invention is illustrated ascircuit 20. Circuit 20 includes a single inductor L coupled betweenswitches S1 and S2 that are operable to switch input voltage for theseparate inputs. In the embodiment illustrated by circuit 20, switch Sswitches +5V input into circuit 20 while switch S2 switches −5V inputinto circuit 20. Switches S1 and S2 are controlled by voltage to dutycycle converters 21 and 22, respectively. Converters 21 and 22 aredriven based on an error signal generated by summing junctions 23 and24, respectively.

Summing junction 24 operates by subtracting an output feedback valuefrom reference voltage Vref to generate an error voltage Verr1. Theoutput feedback value is determined from output voltage +Vout multipliedby a feedback ratio β. Accordingly, summing junction 24 realizes theerror voltage feedback equationVerr1=Vref−(+Vout*β).Error voltage Verr1 generated at the output of summing junction 24 isapplied to duty cycle converter 22 to produce the appropriate switch onand off times for switch S2.

Summing junction 23 operates by subtracting an output feedback relatedvalue from output feedback −Vout multiplied by feedback ratio −β togenerate an error voltage Verr0. The output feedback related value isdetermined from output voltage +Vout multiplied by a feedback ratio β.Accordingly, summing junction 23 realizes the error voltage feedbackequationVerr0 =(−Vout*−β)−(+Vout*β).The resulting error voltage is applied to duty cycle converter 21, toproduce the switching control signals for switch S1.

According to an aspect of circuit 20, the voltage feedback configurationcan be viewed as the combination of a differential voltage feedback anda common mode voltage feedback to achieve the desired control signalsfor switches S1 and S2. Summing junction 24 compares positive outputvoltage +Vout with voltage reference Vref to provide a common modefeedback signal. Summing junction 23 compares negative output voltage−Vout with an inverted positive output voltage +Vout to obtain adifferential mode feedback signal applied to duty cycle converter 21. Byusing both common mode and differential mode feedback to controlswitches S1 and S2, a simple, balanced and robust control for a dualoutput buck-boost converter is obtained.

Circuit 20 operates by generating a feedback control from positiveoutput voltage +Vout based on a comparison with reference voltage Vref.A feedback from negative output voltage −Vout is inverted and comparedto positive output voltage +Vout. In addition, the polarity of thecomparison at summing junction 23 is opposite to the polarity providedat summing junction 24. If positive output voltage +Vout changes beyonda desired threshold or range, duty cycle converter 22 applies a dutycycle control to switch S2 to vary the pulse widths of switch S2. Ifpositive output voltage +Vout is greater than desired, the pulse widthsapplied to switch S2 are reduced. Similarly, if positive output voltage+Vout is to be increased, the pulse widths applied to switch S2 areincreased as well. This scenario follows the conventional controlmethodology.

In the case of negative output voltage −Vout, duty cycle converter 21applies a pulse width control to switch S to increase or reduce outputvoltage −Vout as desired. However, an increase in the magnitude ofnegative output voltage −Vout is achieved by reducing a pulse width ofswitch S1, while a reduction in the magnitude of negative output voltage−Vout is obtained by increasing a pulse width of the control applied toswitch S1. Surprisingly, this result is achieved by applying a controlthat appears to be opposite to that which would otherwise be intuitive.That is, the desired result is achieved by controlling pulse width in anopposite relationship to that of the desired direction of negativeoutput voltage change.

Relative switching times for switches S1 and S2 are similar if changesto output voltages +Vout and −Vout occur simultaneously. For example, ifoutput voltages +Vout and −Vout both increase at the same time, or withthe same magnitude, the respective pulse widths for switches S1 and S2decrease together. If the output voltages +Vout and −Vout both decreaseat the same time, or with the same magnitude, the control for circuit 20increases the pulse widths for both switches S1 and S2. Thecorresponding increases or decreases in pulse widths produce desiredincreases or decreases in both outputs +Vout and −Vout.

If there is a difference in the magnitudes of output voltages +Vout and−Vout, the pulse widths applied to turn on switches S1 and S2 becomeunequal to compensate for the difference in output voltages. If themagnitude of positive output voltage +Vout becomes greater than themagnitude of negative output voltage −Vout, the pulse width of thesignal applied to turn on switch S1 becomes shorter. Shortening thepulse applied to switch S1 creates an uneven switching event withrespect to the on times of switches S1 and S2. Accordingly, when switchS2 is on and switch S1 is turned off due to the shortened pulse width,current flows in circuit 20 from negative output voltage −Vout tonegative input voltage −Vin, thereby increasing the magnitude ofnegative output voltage −Vout. During this event, inductor L isenergized with the current flowing from output voltage −Vout to inputvoltage −Vin.

If the magnitude of negative output voltage −Vout becomes greater thanthe magnitude of positive output voltage +Vout, the pulse width of theswitching signal applied to switch S1 becomes longer. Accordingly,switch S1 stays on while switch S2 is switched off in this circumstance.With switch S1 on, current flows from positive input voltage +Vin topositive output voltage +Vout, thereby increasing the magnitude ofpositive output voltage +Vout. Again, current flowing from positiveinput voltage +Vin to positive output voltage +Vout tends to chargeinductor L.

In each of the cases where the positive and negative output voltagesdiffer in magnitude, inductor L is energized because of theconfiguration of switches S1 and S2. In each instance, current flows inthe same direction through inductor L, thereby storing energy that isredistributed to outputs +Vout and −Vout as the difference between themagnitude of the output voltages decreases. Accordingly, the efficiencyof circuit 20 is very high, and power is provided to each of thepositive and negative outputs with each switching cycle.

Referring now to FIG. 3, another embodiment of the present invention isillustrated as circuit 30. Circuit 30 includes two complimentary bipolartransistors 33, 34 that operate as switches S1 and S2 according to theprevious embodiment discussed above. Switch 33 is a PNP transistor,while switch 34 is an NPN transistor. It should be apparent that anyappropriate types of switches and associated components may be used. Forexample, Two MOSFET switches may be used in place of each bipolar switch33, 34, to maintain bi-directional switching with reduced on resistance.

Switches 33, 34 and diodes D1 and D2 are illustrated as being containedwithin IC 35. Control circuitry within IC 35 includes a feedbackattenuator and reference generator block 38 for generating referencevoltage Vref and feedback voltages +Voref and −Voref. Feedback voltage+Voref represents positive output voltage +Vout, as conditioned by block38. Similarly, feedback voltage −Voref represents negative outputvoltage −Vout, again conditioned by block 38. Feedback voltage +Voref isdelivered to the inverting inputs of comparator/summer blocks 41 and 42in accordance with the present invention. Negative feedback voltage−Voref is provided to the non-inverting input of comparator/summer block41 alone. Blocks 41 and 42 provide pulse width conversion operationbased on the comparison/summer results, and operate switches 33 and 34accordingly. A clock divider and ramp generator 36 provides the waveforms used to develop the pulse signals provided to switches 33 and 34.

IC 35 has outputs connected to positive input voltage +Vin and negativeoutput voltage −Vin, positive output voltage +Vout and negative outputvoltage −Vout, and inductor L. Accordingly, IC 35 can match thefootprint and functional connectivity provided by prior conventionalbuck-boost converters with dual outputs. A significant difference in theconnections provided to IC 35 is the connection of a single inductor Lwhere previously two different inductors were connected. Accordingly,the present invention realized in IC 35 can provide a simple replacementsolution in dual output power converters that need only have a singleinductor coupled to IC 35.

Referring now to FIG. 4, a series of graphs illustrating operation ofcircuits 20 or 30 is illustrated. Graph 40 illustrates inductor currentover the course of a switching cycle in which negative output voltage−Vout has surged in a negative direction, or has an increased magnitudewith respect to positive output +Vout. Positive output voltage +Vout hasnot changed. The overall width of the interval where current is flowingthrough inductor L is represented as W in graph 40. The various slopesof the currents through inductor L are indicated on graph 40, with aninitial slope of (+Vin-−Vin)/L. The second slope of inductor current isgiven as (+Vin-+Vout)/L. The third slope illustrated in graph 40 isgiven by (−Vout-+Vout)/L. The period during which switches S1 and S2 areconducting are illustrated as D+ and D−, respectively. The components ofgraph 40 are illustrated in graphs 41-44 to assist in the explanation ofthe operation of circuits 20 and 30.

Graph 41 illustrates the negative input voltage −Vin current in switchS2 or switch 34, indicated as D−. Because the switching interval forswitch S2 or switch 34 does not change when negative output voltage−Vout surges in the negative direction, the initial ramp ends at a timeconsistent with the value of reference voltage Vref. However, becausenegative output voltage −Vout has a greater magnitude than positiveoutput voltage +Vout in this example, the interval of D+, or when switchS1 or switch 33 is on, becomes longer. The longer pulse width for switchS1 or switch 33 is partially due to the polarity of the comparisonbetween positive output voltage +Vout and negative output voltage −Vout.Accordingly, graph 42 illustrates switch S1 or switch 33 being turned onlonger than switch S2 or switch 34, so that interval D+ exceeds that ofinterval D−.

Graph 43 illustrates the current through diode D2, which matches theprofile of inductor current illustrated in graph 40 for that interval.The interval is indicated in graph 43 as W-D−. Similarly, graph 44illustrates the current through diode D1, which occupies a smallerinterval than the current through diode D2 illustrated in graph 43. Thecurrent through diode D1 in graph 44 exists for a shorter period oftime, so less charge goes to capacitor C2 than goes to capacitor C1.Accordingly, the magnitude of the negative output voltage −Vout isreduced, and the surge on the negative output is corrected. Completecorrection of the voltage surge can occur over a number of cycles inaccordance with the control of the present invention.

While FIG. 4 illustrates the case where the magnitude of the negativeoutput voltage −Vout has increased above the magnitude of the positiveoutput voltage +Vout, the other cases of differences between the outputvoltages are readily determined. For example if negative output voltage−Vout decreases in magnitude towards zero relative to positive outputvoltage +Vout, then the interval indicated as D+ in graph 42 willdecrease below the interval D− indicated in graph 41. The intervalillustrated as W-D+ in graph 44 will increase and more charge will go tocapacitor C2, thereby pushing up the magnitude of negative outputvoltage −Vout. As a negative output voltage is corrected, the circuit isagain in balance and complete correction can be obtained in one or morecontrol cycles.

With respect to positive output voltage +Vout sagging or surging,interval D− illustrated in graph 41 will increase or decrease,respectively, to correct the error. At the same time, interval D+illustrated in graph 42 adjusts to have negative output voltage −Vouttrack with positive output voltage +Vout, as occurs in the casesdescribed above. In instances where both positive and negative outputssag or surge together, both intervals D− and D+ illustrated in graphs 41and 42 will increase or decrease, respectively. The interval W duringwhich inductor L is conducting current is typically shorter than theswitching cycle period, while the power converter runs in discontinuousmode.

It should be apparent that while the present invention is illustrated ashaving positive output voltage +Vout applied to the feedback for controlof negative output voltage −Vout, the opposite configuration is alsocontemplated within the scope of the present invention. That is, ifnegative output −Vout were applied as a reference in the feedback forpositive output voltage +Vout, the tenets of the present invention wouldstill hold true, with the accompanying changes in polarity for thesumming junction.

Although the present invention has been described in relation toparticular embodiments thereof, other variations and modifications andother uses will become apparent to those skilled in the art from thedescription. It is intended therefore, that the present invention belimited not by the specific disclosure herein, but to be given the fullscope indicated by the appended claims.

1. A power converter circuit, comprising: (a) first and second inputsfor connection to first and second input voltage sources, respectively;(b) first and second nodes for connection to terminals of an inductor;(c) a first switch between said first input and said first node; (d) asecond switch between said second input and said second node; (e) firstand second power outputs coupled to said first and second nodes,respectively; and (f) a controller for said first and second switches,said controller operable to control said first switch in response to afirst error signal determined by a voltage at said first output and areference voltage, and said controller operable to control said secondswitch in response to a second error signal determined by said voltageat said first output and a voltage at said second output.
 2. The powerconverter circuit of claim 1, wherein said controller includes first andsecond voltage-to-duty-cycle converters with outputs for said first andsecond switches, respectively, and with inputs for said first and seconderror signals, respectively.
 3. The power converter circuit of claim 2,wherein said first error signal is determined as said reference voltageminus said first output voltage scaled by a feedback factor, and saidsecond error signal is determined as said second output voltage invertedand scaled by said feedback factor minus said first output voltagescaled by said feedback factor.
 4. The power converter circuit of claim1, wherein said first switch is an npn transistor, said second switch isa pnp transistor, a first diode connects said first output to said firstnode, and a second diode connects said second output to said secondnode.
 5. A dual buck-boost converter, comprising: (a) first and secondinputs connected to negative polarity and positive polarity inputvoltage sources, respectively; (b) first and second nodes connected toterminals of an inductor; (c) a first switch between said first inputand said first node; (d) a second switch between said second input andsaid second node; (e) positive polarity and negative polarity poweroutputs connected through first and second diodes to said first andsecond nodes, respectively; and (f) a controller for said first andsecond switches, said controller operable to control said first switchin response to a first error signal determined by a voltage at saidpositive polarity output and a reference voltage, and said controlleroperable to control said second switch in response to a second errorsignal determined by said voltage at said positive polarity output and avoltage at said negative polarity output.
 6. A method of powerconversion, comprising the steps of: (a) determining a first errorvoltage as V_(REF)−β*V_(OUT+) where V_(REF) is a reference voltage, β isa feedback factor, and V_(OUT+) is the voltage at a positive polarityoutput; (b) determining a second error voltage as −β*V_(OUT−)−β*V_(OUT+)where V_(OUT−) is the voltage at a negative polarity output; (c) usingsaid first error voltage to drive a first voltage-to-duty-cycleconverter to control a first switch where said first switch connects anegative polarity input to a first terminal of an inductor and through adiode to said positive polarity output; and (d) using said second errorvoltage to drive a second voltage-to-duty-cycle converter to control asecond switch where said second switch connects a positive polarityinput to a second terminal of said inductor and through a diode to saidnegative polarity output.